1. Field of the Invention
The present invention relates to a semicustom semiconductor integrated circuit, and more specifically, an input/output circuit for use in a peripheral block of a semicustom semiconductor integrated circuit such as a gate array IC (integrated circuit) composed of CMOS (complementary metal-oxide-semiconductor) transistors.
2. Description of Related Art
In the prior art, a gate array IC composed of CMOS transistors includes not only an internal CMOS gate array but also a peripheral block which includes power supply pads, signal input/output pads and various elements for constituting external signal input circuits, internal signal output circuits, and signal input/output circuits. For this purpose, each unitary circuit of the peripheral block includes a bonding pad, a resistor and a diode used for constituting an external signal input circuit, a pair of P-channel transistor and N-channel transistor having a large channel width for constituting the output circuit, and a group of P-channel MOS transistors and N-channel MOS transistors which have a channel width similar to those of transistors of an internal CMOS gate array and which are used to constitute a different kind of peripheral circuit.
In one typical unitary circuit of a peripheral block of conventional semicustom CMOS gate array ICs, an input/output pad, a polysilicon resistor and a junction diode used for forming an input protection circuit, an N-channel MOS transistor and a P-channel MOS transistor of a large size used to form an output buffer, and a group of P-channel transistors and another group of N-channel transistors used for realizing various functions for an input or output circuit, are arranged in a peripheral region of an IC chip in the name order starting from a peripheral edge portion of the IC chip towards an internal CMOS gate array of the IC chip. In this connection, it should be noted that the polysilicon resistor and the junction diode are of a relatively large size in order to ensure an input protection function.
In the case of forming an input protection circuit in the above mentioned unitary circuit of the peripheral block, the input/output pad is connected to one end of the polysilicon resistor, which is connected at its other end to one end of a cathode region of the junction diode. The other end of the cathode region of the junction diode is connected to an internal circuit through a wiring conductor. Thus, the input protection circuit composed of the polysilicon resistor connected at its one end to the input pad and a resistor composed of the cathode region of the junction diode and connected at its one end to the other end of the polysilicon resistor and at its other end to the internal circuit. A connection node between the polysilicon resistor and the resistor composed of the cathode region of the junction diode is grounded to the junction diode itself which is in a reversed direction from the connection node toward the ground. In the above mentioned input protection circuit, however, the N-channel MOS transistor and the P-channel MOS transistor of the large size are not used at all and put in an unconnected condition.
On the other hand, in the case of forming an output circuit in the above mentioned unitary circuit of the peripheral block, the input/output pad is connected commonly to a drain of the N-channel MOS transistor of the large size and a drain of the P-channel MOS transistor of the large size. A source of the P-channel MOS transistor of the large size is connected to a high voltage line, and a source of the N-channel MOS transistor of the large size is grounded or connected to a low voltage line. Gates of the N-channel MOS transistor and the P-channel MOS transistor of the large size are commonly connected to an output of an internal circuit. Thus, a CMOS inverter having a high current capacity is formed of the N-channel MOS transistor and the P-channel MOS transistor of the large size. In this case, however, the polysilicon resistor and the junction diode are not used at all and put in an unconnected condition.
As seen from the above, each unitary circuit of the peripheral block of the conventional semicustom CMOS gate array ICs has not only the input/output pad, but also the polysilicon resistor and the junction diode used for forming the input protection circuit, and the N-channel MOS transistor and the P-channel MOS transistor of the large size used to form the output buffer. Therefore, the peripheral block requires a substantial device area, since not only the N-channel MOS transistor and the P-channel MOS transistor used to form the output buffer are of the large size but also the polysilicon resistor and the junction diode must have a relatively large size allowing a large current to flow therethrough for protecting the internal circuit from a large voltage. As a result, in the case that the number of internal circuits is small but the number of peripheral blocks are large, a ratio of the area of all the peripheral blocks to an area of the whole IC chip inevitably becomes large. Namely, the integration density cannot be elevated.